Griffin is expected to contain at least 2MB of L2 cache, with each core having 1MB all to itself. The two cores will be able to run at different clock speeds, allowing either or both to slow down - as far as 300MHz - when their workload lightens. Griffin's northbridge circuitry combines the usual HyperTransport 3 controller and a DDR 2 memory manager capable of handling 667MHz and 800MHz memory, AMD has said in the past. These elements and the CPU cores all operate on separate voltage planes, to allow unneeded components to power down.