Two companies are gearing up new capabilities that can help software automatically take advantage of today's multicore processors. The MathWorks has built new parallel processing techniques into its flagship MatLab environment, and startup Exludus Technologies, Inc. (Montreal) is preparing an enhanced release of its scheduling middleware for multicore X86 servers. The efforts mark two small steps on the way toward tackling the grand challenge in computing today: Creating an easy-to-use approach for software to fully use the many cores and threads supported on the latest microprocessors.

The five chips run at clock speeds ranging from 1.7GHz to 1.9GHz. Three of the chips -- the 2344 HE, 2346 HE, and 2347HE -- are designed for servers with two processors, while the other two -- the 8346 HE and 8347 HE -- can be used in servers with four or eight processors. They are priced from $255 to $873 in 1,000-unit quantities, a standard way of quoting chip prices.

It is pretty clear why AMD focused on the server market. Without a complete redesign it is not possible to beat Intel's integer crunching power and the fast and big L2-cache and that is exactly what a modern game needs. Barcelona build further on the K8 architecture and inherited the relatively inflexible integer pipeline. While Core 2 has sophisticated reordering of loads and stores, Barcelona does a limited reordering of loads. While Core 2 offers a 32 entry queue to the integer units, Barcelona has 3 rather inflexible separated 8 entry queues. So the right way forward for AMD was to focus on HPC and server applications where it could leverage it's strong points. We can bash AMD for being so late, and coming up with relatively low clocked CPUs, but even a 2.8 GHz Phenom would not have raise AMD's ASP significantly in the desktop market. We can tell you that we are almost done with our first round of quad socket benchmarking and we can tell you that we are having a lot more fun than Anand: it is good old exciting fight between AMD and Intel. Don't believe us? Let intel do the talking again.

Johan knows his stuff. The ZDNet bloggers don't. It is that simple.

Traditionally, it takes more than six months to make core and transistor changes, but with CTI AMD can do it within six months. This dynamic of processor tweaks was present from the launch of Barcelona and judging from the fact that B3 revision was ready in March, you should expect a new and slightly improved 65nm core by autumn (fall) time.

CTI is continuous transistor improvement. Then they discuss AMD using a direct connect module on their upcoming 12 core CPU, Magny-Cours.

Intel uses MCM, Multi-chip module, connects two cores dual-cores in quad-core and it uses Northbridge to talk to the chip; while AMD will use its own Direct Connect Module approach. Before we start to explain how this actually works, let us underline that AMD will use two six-core Sao Paolo chips to make the 12-core Magny-Cours, but as we said, in its own way. AMD’s Direct Connect Module uses coherent Hypertransport link to interconnect the cores. It all happens in the chip and AMD doesn’t need a Northbridge for the inter-chip communication, at least not the way that Intel does, and therefore makes things faster.

Lastly there is word that AMD's Suzuka core will support DDR3 in Q2 of 2009.

The new 45nm quad-core is codenamed Suzuka and it has 6MB L3 memory 1xHT3 and AMD-V support. The big difference between Shanghai and Suzuka is the memory support and the use of a different socket. Suzuka will be AMD’s first CPU to support DDR3 memory.