Patla asserted that Shanghai is a "very power efficient product" and will perform much better than Barcelona because the smaller 45-nanometer process yields "a lot more (clock) frequency." At the same frequency (speed), Shanghai will outperform Barcelona by about 20 percent, Patla said. AMD is also boosting the size of the cache memory, which typically speeds performance, from 2 megabytes to 6 megabytes. "We're also turning on HT3 (HyperTransport 3) and you'll see partners start to validate that in the Q1 time frame," Patla said. HyperTransport is a high-speed communication link technology between silicon.

So here we see a 20% clock for clock improvement claimed, and more clock claimed to be coming as well. We will see.