The most common way, one would think, is to reduce the clock speed to 1.8GHz, down from the Athlon 64 Model 3200+'s 2GHz, and keep all the other performance-related goodies intact. We were adamant that this would be the case. AMD, however, decided on a different course of action for the Model 3000+. In true AMD style, the CPU's performance rating doesn't necessarily tie in with clock speed changes. Intrigued?, we were. Let's find out a little more about the current baby of the Clawhammer clan.

You can grab the boxed 3000+ here for $217.

In the nine or so years since the IA-64 design was publicly known, its primary aim seems to have been discouraging all high-performance RISC vendors from continuing their independent designs. With all the hype and promises of unbeatable performance and features, backed by the almighty Intel machine, well it was like no choice, wasn't it? Either you sign with the behemoth at the "paper tiger" stage, or you'll be trampled upon when the time comes, you'll be history. So, Alpha, HP-PA and MIPS were "voluntarily killed" to make way for the Itanic. All that despite many knowing about the (few) pros and (many) cons of the newest kid on the block.

The FX-55 ought to provide an early demonstration of why we have for the longest time suggested that people wait for 90nm Hammers before leaving their socket A platforms.

So it is quite conceivable that somebody speaking to Digitimes might have said that Newcastles would be available at speeds from 1.8GHz-2.4GHz, but somewhere lost in the confusion was the detail that half of them are socket 754s and half are socket 939s.

Oh, put your Kleenex away. Remember, the name of the game is not the number of bits, the clock speed, or the size of the cache. It?s throughput. Intel likes to put a lot of silicon between its CPUs, memory, and I/O bus. AMD?s design focuses on direct (?glueless?) links among up to eight CPUs in a multiprocessing system. Opteron?s on-CPU memory controllers can give each processor a dedicated bank of RAM so that it spends less time waiting for a single pool of memory that?s shared among all CPUs. Opteron?s memory and inter-CPU buses operate independently, thereby removing the stoplights inherent in, shall we say, familiar designs that stack up I/O requests in single file. Before you go sticking forks in AMD, wait for some throughput numbers. As Intel has said, just slapping 64-bit instructions on a 32-bit processor doesn?t buy you much. It?s a good thing AMD didn?t do that.

Waiting for throughput numbers? The ones from last April? I'm at a loss. I expect better than this out of Infoworld.