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Innovative Silicon Unveils Z-RAM Memory Technology Breakthroughs at 2008 IEEE International SOI Conference |
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Written by Chris Tom
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Thursday, 09 October 2008 16:52 |
Smallest Silicon Dynamic Memory Devices Ever Reported
Largest Programming Window, Significantly Improved Retention Time Demonstrated
2008 IEEE International SOI Conference
NEW PALTZ, N.Y.--Innovative Silicon, Inc. (ISi), developer of the Z-RAM® zero-capacitor floating body memory technology, demonstrated here that its Z-RAM memory technology continues to show considerable advantages over DRAM implementations and other proposed floating body memory designs. Dr. Mikhail Nagoga, a principal member of ISi’s technical staff, presented a paper written by Dr. Serguei Okhonin, chief scientist at ISi, that describes the smallest silicon dynamic memory devices ever reported, with the largest programming window. Separately, Dr. Ammar Nayfeh, a member of ISi’s technical staff, presented a paper that discusses improvements in Z-RAM memory retention times and a reduction in leakage current.
In the paper delivered by Nagoga, titled “Ultra-scaled Z-RAM cell,” Z-RAM cells based on Multiple-gate SOI MOSFETS (MUGFETs) with gate lengths down to 50nm and fin widths down to 11nm were demonstrated for the first time. Simulations proved that the basic operational principles are effective on Z-RAM cells with gate lengths down to 12.5nm and fin widths of 3nm.
Further analysis also shows that these devices exhibit the largest programming window (margin) ever recorded. Measured as the difference in current between STATE 1 and STATE 0, the programming window of these MUGFETs is close to 22µA.
Okhonin commented, “Even such small devices demonstrate a reliable memory effect, and the experimental data presented in the two papers indicates the excellent scalability of our Z-RAM memory devices. Furthermore, the results we demonstrated today are only achievable in floating body architectures. We believe our transistors are not only the smallest silicon dynamic memory devices ever published, but also the best performing. Moreover, at equivalent gate lengths, we demonstrated a several times larger programming window than previously published.”
Nayfeh’s paper, co-authored with ISi fellow Dr. Victor Koldyaev and titled, “A Leakage Current Model for SOI based Floating Body Memory that Includes the Poole-Frenkel Effect (PFE),” describes for the first time how the leakage current of SOI based floating body memory has been modeled and compared to experimental Z-RAM data, taking into account oxide/SOI Dit and PFE. The model has enabled the Z-RAM design team to significantly reduce the number of defects per cell, leading to an increase in retention times and a reduction in leakage current.
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Innovative Silicon Z-RAM News |
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Written by Chris Tom
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Friday, 03 October 2008 08:27 |
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Marketwatch reports that Innovative Silicon will be presenting at the 2008 IEEE International Universal SOI conference. Z-Ram is what they have, and AMD has a license for it. It could be used for the cache on their CPUs. When or if this will happen is unknown, but maybe we can get some clues from this talk. |
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Futuremark Favors GenuineIntel? |
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Written by Matthew Cameron
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Wednesday, 30 July 2008 20:38 |
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Does Futuremark favor processors that simply have a GenuineIntel CPUID? Ars Technica thinks so, at least, for the PCMark 2005 benchmark. While both AMD and Intel lock their CPUID, VIA does not, therefore allowing someone with a VIA chip to change CPUIDs to reflect that of an AMD or Intel processor. When this is done on the VIA NANO chip, the results speak for themselves. On the memory test, when the NANO is seen as an AMD processor, it scores roughly 10% more than it normally would have. Yet, when it has an Intel CPUID, the score goes up almost 50%! I'll give Futuremark the benefit of the doubt and say that this is just bad coding. |
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