What AMD said doesn't make a whole lot of sense unless DDR/DDR2 support is an either/or proposition. If supporting DDR2 is just a matter of adjusting the memory controller a bit, the best time to change the silicon would be when they went to 90nm.

AMD will support DDR2 when it makes sense
- When DDR2-667 is introduced and performance advances enough to overcome the DDR2 latency penalty
- When the DDR2 price premium fades

At the time of the Prescott launch, we updated the BIOS of the SK8N to rev 1004. We double-checked all the memory timings, which looked good -- CAS 2-3-2-7, which was the most stable setting. The memory clock read 200MHz, so all was well and good.

Well, no. You see, when the SK8N BIOS reads "200MHz", it really means "200MHz DDR." The memory clock was really set to 100MHz. There's no standard way to specify this in the motherboard world, but I'd gotten used to seeing actual clock rates in most BIOSes. When you see "166MHz", you'd know that the memory setting was for 333MHz DDR, for example. But it turns out that Asus meant "200MHz DDR". You know what they say about getting too comfortable?

He said AMD had a good idea of when that point might be, but would not confirm that could happen in 2005. Plus, AMD believes that it is already getting a burst of speed because of the integration of memory technology in its 64 bit chips.

Sunnyvale, CA , March 11, 2004 ? OCZ Technology Group, a worldwide leader in innovative, ultra high-performance memory solutions for PC enthusiasts and gamers, today announced it has developed Enhanced Bandwidth (EB) technology to deliver improved DDR bandwidth. OCZ also announced the release of several new DDR memory products featuring the new EB technology.

OCZ EB technology builds on optimal usage of DDR command structures to warrant continuous data transfers regardless of the CAS latency of the memory components. This scheme can be extended beyond CAS latency values used in current DDR DRAM technology.

OCZ EB technology challenges conventional wisdom that implicates increased CAS latency as the main factor causing reduced effective bandwidth. OCZ engineers have shown that by reducing the latency cycles associated with the precharge-to-activate delay and the RAS-to-CAS delay along with the use of the Variable Early Read Command feature of DDR, higher effective data bandwidth is possible.

?Enhanced Bandwidth technology is an exciting improvement that, at 2.5-2-3 (CL-tRP-tRCD) latencies, allows most applications to use data bandwidth that is the same as that delivered by CL-2 modules,? said Dr. Michael Schuette, OCZ director of technology development. ?By extension, this means that OCZ memory modules provide the most efficient DDR solution available in the retail channel.?

OCZ is releasing several new products featuring the new EB memory in its Platinum series. OCZ is offering PC-3200 and PC-3500 unbuffered DDR memory in 256 MB, 512 MB and 1 GB single modules. Paired EB DDR memory is also available in 512 MB (2x256), 1 GB (2x512), and 2 GB (2x1024) kits.

Read our detailed whitepaper on Enhanced Bandwidth technology here.