Want to see our Roadmaps and Bulldozer Info?

[abinstein]

I think it is like in Dresdenboy's schemas, because I strongly assume that these 4 piplines are 2 AGUs + 2 ALUs. 4 INT pipes would we too much, the sweet spot is 2 Futhermore, if you want to feed 4+4 ALUs and 2x128 bit FMACs, too then you would need a hell of a front end

Last but not least, the Bobcat core has 4 pipelines, too:

Bobcat is not Bulldozer, and I believe they are designed differently.

For example, in the FPU, the A-pipe and M-pipe apparently mean [edit]addition and multiplication[/edit] pipelines. These don't make sense in the Bulldozer graph, where both pipelines are 128-bit FMAC.

The explicit load & store pipelines are probably also specific to Bobcat for power efficiency and simplicity (IIRC this is what Pentium-M did, which propagated to Core and even Core2 as well).

There is really no reason for Bulldozer to have separate pipelines for AGU. Currently, K10 already has an AGU attached on each ALU; this architecture works quite well for x86 instructions where most instruction is attached with a load/store. There's little reason to change that. But, it's just my guess, and I could be wrong.

What I do know is that AMD's instruction decode was designed originally for 4-way. Previously, it's not useful to go above 3 because each cycle the fetch unit only gets 16 bytes. In k10, the width is increased to 32 bytes and there will be opportunities to decode 4 instructions per cycle. Whether it's practically feasible is unknown, though.

[wuttz]

head to head in 2011


*ivy bridge is a 22nm shrink of this.

vs.




.or more appropriately..

?

[kairi_zeroblade]

thats why intel must NOT reuse or EITHER make a new acrhitecture..they are just basing it on their old architecture..yet its not even wise to say its something NEW..

[hyc]

50GB/sec memory bandwidth, pretty darn cool. So I have to ask the next obvious question - will the physical and virtual address space be increasing in 2010 or 2011? I'm designing an in-memory transactional database now, it would happily use 1TB if you could cram that into a single node. Memory capacity is another bottleneck, not just memory speed and bandwidth...

[kairi_zeroblade]

buldozer in a way is much effective since each thread you make gets a core for itself and each core gets 4 pipes i believe that on x86 based process this is uniquely effective..plus not to mention if they intend to use CMT on it..do they??..unlike HT you suck in 2 threads on 1 core which gives a performance loss unless you clock higher..and its found to have some issues like processing gaps..

[wuttz]

buldozer in a way is much effective since each thread you make gets a core for itself and each core gets 4 pipes i believe that on x86 based process this is uniquely effective..plus not to mention if they intend to use CMT on it..do they??..unlike HT you suck in 2 threads on 1 core which gives a performance loss unless you clock higher..and its found to have some issues like processing gaps..

two integer cores sharing one fpu IS cmt.

[kairi_zeroblade]

two integer cores sharing one fpu IS cmt.

cute..

[MTd2]

What else did you need to know?

AMD fusion products were taped out
http://www.semiaccurate.com/2009/11/11/ ... has-moved/

So, is there a chance for a fusion release next year?

[MKruer]

What else did you need to know?

AMD fusion products were taped out
http://www.semiaccurate.com/2009/11/11/ ... has-moved/

So, is there a chance for a fusion release next year?

Probably not, The reason is AMD needs to to a extra long validation process. This is a ground up new design. the K10 and its variants got around this because the fundamental arch was the same and the original K10

[Raqia]

Will the southbridge be on die for the first batch of Bulldozers?

[Valerón]

Why is new architecture still sitting on pretty old sockets?
Highly doubt that old sockets won't become bottleneck. Same for C32 and AM3r2.
Since Intel has armed with up to 4 channels on server and 3 channels on high-end desktop.
Is AMD so sure bulldozer@2 can win over sandybrige@3?(maybe 4 if intel's insane and ddr3 prices goes down greatly)

btw, G34 is also 1207 pins, but can do up to 4 channels. Is it actually with new pins definition and completely incompatible with the 1207 nowadays?

[Эльбрус]

Bobcat is not Bulldozer, and I believe they are designed differently.

Of course, I just wanted to point on AMDs naming procedures. With BUlldozer they just stated "pipeline", with Bobcate they explicitely said 2xINT plus 1Ld, 1 str. pipelines. Therefore I think it will be the same with Bulldozer. 4way would be also too much for 1 core. 2way is the optimum from a cost/performance stand point. If you would have 4 way, you would need SMT again to be able to utilize all the pipelines optimally.

For example, in the FPU, the A-pipe and M-pipe apparently mean [edit]addition and multiplication[/edit] pipelines. These don't make sense in the Bulldozer graph, where both pipelines are 128-bit FMAC.

Read carefully, AMD said nothing about Pipelines in the FPU part. They just wrote 2x128bit FMAC. Thus they mean the ability to process two 128bit FMAC µOPs. How this is done in detail is not know yet, but there is a patent at Dresdenboy's blog which covers that, too

The explicit load & store pipelines are probably also specific to Bobcat for power efficiency and simplicity (IIRC this is what Pentium-M did, which propagated to Core and even Core2 as well).

I speculate that they just referred to 2 AGUs. Why should they change so much compared to the K8 ? If AMD would use explicit Ld/Str pipelines and now AGUs, then they would have to re-engineer the µOp sub-system, too. If I would be AMD, I would be too lazy to do that
A K8 core itself is already quite energy efficient and small at 32nm, now if you cut it down to 2way it is 99% perfect A further re-work would not gain much.
But as I said - speculation only. Maybe AMD did indeed a lot of µOp rework - who knows.

There is really no reason for Bulldozer to have separate pipelines for AGU. Currently, K10 already has an AGU attached on each ALU; this architecture works quite well for x86 instructions where most instruction is attached with a load/store. There's little reason to change that. But, it's just my guess, and I could be wrong.

Yes - no reason to change that, I agree totally
We then just differ in the counting method for pipelines In my opinion you could count the AGUs as independent pipelines, thus 2 INT+2 AGUs per core = 4 "pipelines". You seem to think that there are 4INT + 4 AGUs, because you count the AGUs not separately. As I stated above, 4 way for one core would be inefficient, therefore I speculate about 2way per core and 4way per module.

Well let's wait and see who is right

What I do know is that AMD's instruction decode was designed originally for 4-way. Previously, it's not useful to go above 3 because each cycle the fetch unit only gets 16 bytes. In k10, the width is increased to 32 bytes and there will be opportunities to decode 4 instructions per cycle. Whether it's practically feasible is unknown, though.

Sounds to me now, that you mix up instruction fetch with instruction decode. The decoders were always 3way only. The prefetch width was increased to be able to decode more 64bit instructions.

@ Valerón:
Because there is no reason for a new socket ... we had that discussion already a few times in the forum, use the search function;-)
And no - G34 is not 1207 pins .. its a "little" bit more

cheers

[abinstein]

@Эльбрус: It's interesting... lets make a bet. Mine is on that there will be 4 INT pipelines (up from 3 in K10) per core in Bulldozer.

I think 2ALU+2AGU is just too few. This is especially true if two cores in a module cannot work on the same sequence of instructions. It has to be 4 ALU+AGU per core. Yes it has to.

Also notice that each INT "core" has its own private L1 data cache. The FPU, however, doesn't seem to have this resource privilege. Does the FPU talk directly to L2 (can't imagine that), or does it share the L1 with both INT cores?

[Эльбрус]

@Эльбрус: It's interesting... lets make a bet. Mine is on that there will be 4 INT pipelines (up from 3 in K10) per core in Bulldozer.

Ha ha, if you want
But be careful, Dresdenboy shares my opinion

Further the 4 int pipelines per core/cluster aren't further detailed, while for Bobcat they are. In the latter case we see 2 ALU + 1 Store + 1 Load pipes. For BD I still think, that we'll see 2 ALU + 2 AGU (combined Load/Store) pipes. Those "multi mode" AGUs would simply fit better to achieve a higher bandwidth and be more flexible, because the FPU will also make use of these pipes.

http://citavia.blog.de/2009/11/11/amd-2 ... y-7353923/

I think 2ALU+2AGU is just too few. This is especially true if two cores in a module cannot work on the same sequence of instructions. It has to be 4 ALU+AGU per core. Yes it has to.

Why ? If there are two different threads then again ... 2way is the cost/benefit optimum

Also notice that each INT "core" has its own private L1 data cache. The FPU, however, doesn't seem to have this resource privilege. Does the FPU talk directly to L2 (can't imagine that), or does it share the L1 with both INT cores?

That is handled like it is already handled with the K8/K10:

Souce: http://www.amd.com/us-en/assets/content ... /40546.pdf

Of course there is L1 access for the FPU but it has to go through the AGUs, too (see also above statement from Dresdenboy).

cheers

[Oliverda]

Why is new architecture still sitting on pretty old sockets?
Highly doubt that old sockets won't become bottleneck. Same for C32 and AM3r2.
Since Intel has armed with up to 4 channels on server and 3 channels on high-end desktop.
Is AMD so sure bulldozer@2 can win over sandybrige@3?(maybe 4 if intel's insane and ddr3 prices goes down greatly)

btw, G34 is also 1207 pins, but can do up to 4 channels. Is it actually with new pins definition and completely incompatible with the 1207 nowadays?

C32 as old socket? It hasn't introduced yet. I'm pretty sure that the sockets won't become bottleneck. Just compare the i5 with dual channel and i7 with triple channel. The difference is tiny (or none) in most cases.
Anyway if the news is true the Bulldozer's destop version will support DDR3-1866 which means ~30GB/s peak transfer rate in dual channel mode.

[JF-AMD]

What else did you need to know?

AMD fusion products were taped out
http://www.semiaccurate.com/2009/11/11/ ... has-moved/

So, is there a chance for a fusion release next year?

Beats me, I am on servers.

[JF-AMD]

Will the southbridge be on die for the first batch of Bulldozers?

No.

[AussieFX]

I have been spending a lot of time on Bulldozer lately, especially with my new job, so we will finally be able to have a conversation about *some* of the details.

What's your new job?

[JF-AMD]

C32 as old socket? It hasn't introduced yet.

C32 is a new socket but it is based on the physical 1207 mechanics. This means that all of the tooling and development costs for the socket have been amortized and it is at a low cost. And partners know how to deal with it because they have been laying out with 1207 for years.

We swapped some pin assignments so that we could support DDR-3 and higher capacities of memory, so current DDR-2 parts will not work in the new sockets. We added some keying on the socket to ensure that 1207 fits in 1207 and C32 fits in C32, no mixing. That reduces the test matrix for customers and prevents them from having to support DDR-3 on older parts.

[JF-AMD]

Why is new architecture still sitting on pretty old sockets?
Highly doubt that old sockets won't become bottleneck. Same for C32 and AM3r2.
Since Intel has armed with up to 4 channels on server and 3 channels on high-end desktop.
Is AMD so sure bulldozer@2 can win over sandybrige@3?(maybe 4 if intel's insane and ddr3 prices goes down greatly)

btw, G34 is also 1207 pins, but can do up to 4 channels. Is it actually with new pins definition and completely incompatible with the 1207 nowadays?

No, for the next year or two Intel is armed with THREE channels on their servers. Only the 4P has 4 channels, and 4P is ~4% of the market. So 96% of the market has only 3 channels and is disadvantaged to AMD.

And the G34 socket has ~1900 pins (I think 1905 but I am home right now and don't have access to the number).

[abinstein]

I think 2ALU+2AGU is just too few. This is especially true if two cores in a module cannot work on the same sequence of instructions. It has to be 4 ALU+AGU per core. Yes it has to.

Why ? If there are two different threads then again ... 2way is the cost/benefit optimum

That would sacrifice the single-threaded performance. It's like going back to the pre-Athlon days with respect to IPC within each thread. Unless both cores can work on the same thread, i.e., there's a unified reorder buffer that do out-of-order issue to both INT schedulers. But again, these two INT cores access different L1 cache, so that option is unlikely.

Also notice that each INT "core" has its own private L1 data cache. The FPU, however, doesn't seem to have this resource privilege. Does the FPU talk directly to L2 (can't imagine that), or does it share the L1 with both INT cores?

That is handled like it is already handled with the K8/K10:

In current design, both INT and FPU share the same L1 cache. In Bulldozer, the FPU has to load data from the L1D cache of either INT cores. The question is which one? Either the load request is sent to both L1 and wait for the coherency to resolve between them, or it is sent directly to L2. In the latter case, however, the cache hierarchy will become inclusive, otherwise it'd be impossible for the INT and FPU to work on the same dataset efficiently. Either way, I can assure you the design is much different from that of K8/K10.

Of course there is L1 access for the FPU but it has to go through the AGUs, too (see also above statement from Dresdenboy).

No you (both) got the wrong idea. Neither FPU nor INT of K8/K10 access memory through AGU. Load-store unit (LSU) is for the purpose. AGU is only used to generate addresses for the complex addressing modes. This is an x86-specific microarchitecture optimization. It doesn't make sense to me to have AGU in a separate pipeline because you'd be basically making a separate ALU whose input & output are not ISA visible. Why go the extra mile of complexity when the AGU can be simply attached to the ALU in the same pipeline?

The "arrow" you see from FPU to INT in the K10 diagram does not mean memory access. It means a fast path of register transfer from the FPU to the INT pipelines. It is one direction only (register transfers at the other direction is ~3x slower).

EDIT: On second thought, what can be simply done is to attach the FP macro-op with a "core#" flag, telling the FPU which INT core this FP operation belongs to. That's probably the simplest way to share an FPU between two INT cores anyway.

[Oliverda]

One thing is not completely clear for me.



This is one Bulldozer module. So, if I'm not mistaken the quad, six or octal core (in the usual sense, so X4, X6, X8) Bulldozer CPUs will contain four, six, or eight Bulldozer module and the OS will detect these as octal, twelve or sixteen core CPUs. Am I right?

[ivanb]

Abinstein and elbrus,I think that we need JF-AMD to talk back to the engineers and if he is allowed ,answer the question about the actual pipeline organization of the one bulldozer module. First question: What does one pipeline segment in the diagram represent?Is each of the 4 listed in Bulldozer module(note: NOT Bobcat) an actual ALU unit or is it 2 ALUs and 2 AGUs? Second question :an issue of decoding ability of the new core while single-threaded code is in question.IF each of the integer mini-cores/clusters inside one module is "only" 2-way(2ALUs+ 2AGUs) will they be able to work on the same sequence of instructions and achieve 4 way decoding ability,ie. both 2 way clusters doing work on one thread? If this is not possible,and one mini-core/cluster IS NOT 4-way(similar to a "true" 4 way Phenom-like decoding ability:4ALUs+4AGUs),what way will AMD use to counter the 4 way decoding ability of say Westmere and SandyBridge cores when single-thread performance is in question? Can 2-way execution of single-thread(or one instruction sequence if you will) be so much efficient that it will be on par with 4 way execution,IF AMD uses a clock gating and clocks the mini-core/cluster much higher than the rest of the module(think 1.5 times the "normal" clock of non-integer units)?

Sorry if the questions are long or too detailed.I hope JF-AMD can at least hint at the way each mini-core inside module is made and what decoding abilities it has and what kind of execution in hardware is possible in single-thread mode(yeah I know single-thread performance is not as important as before and that it is yesterday news,but for client computing it still is important).

[BaronMatrix]

Why is new architecture still sitting on pretty old sockets?
Highly doubt that old sockets won't become bottleneck. Same for C32 and AM3r2.
Since Intel has armed with up to 4 channels on server and 3 channels on high-end desktop.
Is AMD so sure bulldozer@2 can win over sandybrige@3?(maybe 4 if intel's insane and ddr3 prices goes down greatly)

btw, G34 is also 1207 pins, but can do up to 4 channels. Is it actually with new pins definition and completely incompatible with the 1207 nowadays?

BD is quad channel. The socket only deals with electrical necessities not the the way the IMC works.

[JF-AMD]

One thing is not completely clear for me.



This is one Bulldozer module. So, if I'm not mistaken the quad, six or octal core (in the usual sense, so X4, X6, X8) Bulldozer CPUs will contain four, six, or eight Bulldozer module and the OS will detect these as octal, twelve or sixteen core CPUs. Am I right?

No.

Interlagos:
12-core = 6 bulldozer modules
16-core = 8 bulldozer modules

OS will see 12 and 16 core respectively.

The Bulldozer module is a logical way to group components and allow for better power efficiency and a more modular scalable path.